We have to design a 0-9 counter for S0 & M0, 0-5 counter for S1 & M1 & 1 – 12 counter for HH. This repeats for as long as the clock runs. The next second it ‘ll become 12:00:00 A. The day passes & now the time is 11:59:59 P. The next second it ‘ll become, 12:00:00 P. So let’s say the time is initially 11:59:59 A.
So when HH becomes 12, A (AM) is changed to P (PM) & vice-versa. So, similar to how when, SS incremented MM when it turned 0 after 59 (it doesnt become 60), MM also should become 00 incrementing HH by 1. The MM counting is similar to SS but MM receives its clock (triggering pulse) from SS. For every 60 seconds, SS ‘ll go to 59 & back to 0, while MM is incremented. Everytime SS reaches 60 a pulse needs to be generated to make M0 one & SS 00.
Whenever S0 reaches 10, a pulse (digital parlance – clock signal) has to be generated to make S0 zero again (digital parlance – reset) & S1 one & the process repeats to make S1 two & so on. So, a 1 second pulse provided to make it count from 0 – 9. M1 & M0 essentially count the same way as seconds. So everytime SS reaches 60, M0 (minutes) should increase by 1. Now when seconds becomes 60, it is one minute. So our S1 counter has to count only from 0-5. So counts from 0 to 9 & then S1 becomes 1 & S0 counts again. Now, SS may also be referred as S1 S0 & the same goes for MM. So, the clock we want is something like this HH : MM : SS A/P. Step 1: The Logic of the Digital Clock Circuit Diagram Digital Clock Circuit DiagramĪs said earlier, our clock is a 12 hour clock. For your kind attention: I ‘ll assume that you know basic high school level digital logic – the fundamental logic gates & binary numbers. The main emphasis however, is learning sequential logic & developing a breadboard based clock using that knowledge. It is not much but I did whatever extra nicks I could do. The alarm is again achieved using IC’s not by programming boards (which quite honestly is comparatively easy). I have only used IC’s but still got a 12 hour clock, which I’ve not seen elsewhere. Next, a process to derive the clock pulse: process(Clk)Ĭlk_pulse Clk, becomes Clk => Clk_pulse.Usual digital clock circuit diagram that are based on decade counters have an hour counter from 0 -23. Note that this is simulation-only code, so you can use initial values however you like. We can easily shorten the clock pulse width to get rid of these oscillations by adding a new 'pulse' signal, derived from the clock: signal Clk_pulse : std_logic := '0' You can now see the oscillations that result from too long a clock pulse in the simulation waveform: To start with, the conventional way to design a JK flip flop in VHDL would look like this: signal Q_s : std_logic
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